The requirement for high speed, high density and high reliability for random access memory chips, especially static random access memory (SRAM) drives efficient and effective test applications to process and manufacture viable components for subsequent incorporation in high end processor products. Manufacturing yield, and ultimately product cost are integral parts of the capability to design, manufacture, and sell computer systems in the marketplace. A key requirement to achieving leading edge technology implementations is the ability to provide for effective testing and diagnostics in the design/manufacturing process, prior to product volume ramp-up. Efficient SRAM/DRAM designs stress the manufacturing process capability. This is because of the high device usage (gates and ultimately transistor elements) in a given area (smaller memory cell yields higher number of bits per chip), and high end processor applications demand high memory bit usage. The drive for high density chips with a large number of gates per unit area results in an increased sensitivity to process defects over the accompanying logic, typically. This drives the need to analyze, understand, and eventually reduce overall process defect density to achieve product yield and cost metrics.
To this end, integrated self test, and particularly for the memory arrays, Array Built In Self Test (ABIST) has been employed to provide deterministic test coverage ensuring high quality products. Assessment of test effectiveness and diagnosis of fails to initial manufacturing test and subsequent stress screens are critical to yield diagnostics and product reliability improvement efforts, as they are more realistic indicators than monitor structures. Monitor structures are easier to diagnose, but are only models of the product/process interaction, and are expensive from the perspective of area overhead and process productivity.
Execution of the ABIST algorithms requires either explicit test programming for micro-programmable architectures, or state machine based algorithms. In ABIST that is synchronous to an external test system, an off-chip fail indicator is monitored, on a cycle-by-cycle basis, to determine at which points in the test the array fails.
In ABIST, the generation of memory/array addressing is accomplished with a single or plurality of sequential counters. These sequential counters comprise the address space of the memory under test and can be divided into appropriate sub-groups representing the row/column and or subarray dimensions of the memory array under test. Current technology provides for incrementing and decrementing the address through the address space of the memory array, and can alter the significance of the address groups i.e. Ripple row addressing as least significant, then column, or ripple column addressing as least significant, then row, to accomplish the intended test sequences. Some systems even provide for maximum address programmability to restrict the count of a wide counter implementation in order to provide self test capability for a plurality of memory array macros that have varying address sizes (width or dimension).
Traditional memory array address space is a full binary function of ‘n’ number of address bits decoded to 2‘n’ cell locations where “n” is a whole number. With the advent of system architectures going to 10 or 12 way set associativity, instead of 8 or 16 way set associativity, or with reduced row/column counts from a traditional binary 64, 128, or 256 boundary, the memory array addressing space follows suit to give an incomplete binary address space. By an “incomplete binary address space” is meant a 2‘j’ address space where “j” is not a whole number.
This process is adequate to provide n-sequential address testing of static memory array RAMs, including SRAMs utilizing clocked operations with memory cell recovery prior to subsequent operations. This is done through the use of binary counters and appropriate control logic, with provisions for division of the address application rate to the memory array device under test (dut). This allows multi-cycle per cell operations whereby a plurality of write or read (e.g. RXWXRX) operations at each addressed location can be reasonably accomplished.
Alternative test methodologies to comprehensively address and test a memory array with an incomplete binary address space, as defined above, may include full binary address space generation, with some form of test result blanking during addressing of the illegal or invalid portion of the address space. Alternatively, a custom counter design may be used to perform increment/decrement function of only the allowable address space. These methodologies all have drawbacks in that either the intended test operations are interrupted with blanked or dead zones in the test methods, or added complexity and performance restrictions in counter design to accommodate the necessary carry/borrow logic to implement a non-uniform address space.
However, the capability to stress controlled address and address group transitions is important in order to test for long time constant effects and to implement low level defect screens in a cost effective and flexible manner.